1. Field of the Invention
The present invention relates to a chip detecting method, and more particularly, to a method of detecting a leading edge blanking parameter of a power management chip.
2. Description of the Prior Art
FIG. 1 is a simplified diagram of a conventional fly-back voltage converter 100. In the fly-back voltage converter 100, a chip 110 outputs a pulse signal via an output pin OUT to control the on/off status of a transistor Q1. By alternately turning the transistor Q1 on and off, the input voltage Vin is converted into the output voltage Vout. In order to prevent the primary current Ip of the fly-back voltage converter 100 from overgrowing and damaging elements of the fly-back voltage converter 100, the chip 110 further detects a voltage level Vcs at a current sensing pin CS. When the voltage level Vcs reaches a predetermined over-current protection reference voltage level, the chip 110 enables an over-current protection mechanism to control the pulse signal outputted from the output pin OUT to shut down the transistor Q1. As a result, the primary current Ip cuts off and the over-current situation is prevented.
However, voltage spikes will be generated when the transistor Q1 is turned on, instantly raising the voltage level Vcs detected at the current sensing pin CS. In this situation, it is easy to mistrigger the over-current protection mechanism to turn off the transistor Q1 without an over-current occurring, affecting the operation of the voltage converter 100. A common solution is to couple a low-pass-filter between the current sensing pin CS and the resistor Rcs. Although the low-pass-filter can decrease interference caused by the spikes to the detecting mechanism of the chip 110, it cannot completely eliminate the spikes; the possibility that the over-current protection mechanism will be mistriggered at the instant the transistor Q1 is turned on still exists. Another solution called “leading edge blanking” is to additionally create a blanking mechanism in the chip 110. The blanking mechanism blanks voltage signals detected by the current sensing pin CS at the instant of turning on the transistor Q1, and therefore the chip 110 will ignore the spikes generated when the transistor Q1 is turned on.
Power management chips having different usages comply with different leading edge blanking standards, but every leading edge blanking standard is designed to appropriately blank the spikes generated at the instant the transistor Q1 is turned on, thus avoiding interfering with the over-current protection function of the power management chip. In implementations, voltage signals detected by the current sensing pin CS are ignored (or the current detection function of the current sensing pin CS is paused) until a predetermined blanking time period passes. Since chips may be affected during manufacturing due to mechanical or artificial factors, an actual leading edge parameter of the chip may differ from the leading edge blanking standard originally designed for the chip. Too large a difference between the actual leading edge parameter of the chip and the leading edge blanking standard will influence the over-current protection in the power system. For example, when the blanking time period is too short, the chip may mistrigger the over-current protection mechanism easily because the spikes are detected; when the blanking time period is too long, an over-current occurrence may be ignored before the over-current protection mechanism is enabled, causing damage to the power system. Therefore, it is necessary to correctly measure a leading edge parameter of a chip, and determine whether the leading edge parameter conforms to the predefined standard of the chip.